1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of forming a thick metal silicide layer on a gate electrode by expanding a contact region between a metal layer and the gate electrode to reduce resistance of the gate electrode.
2. Description of the Related Art
In recent years, as cells are becoming smaller in size, semiconductor devices are more efficient in performance. However, as the design rule of semiconductor devices has been reduced to 0.1 μm or less, the fabrication process becomes more complicated. For example, it is difficult to isolate devices in a cell, pattern a gate electrode to 0.1 μm or less, perform source/drain engineering, form a reliable contact structure, and pattern a first metal layer (metal-1).
Fabrication of a semiconductor device comprises forming a transistor followed by forming a metal contact structure and a first metal layer (metal-1). Here, a circuit is structured such that the transistor is operated when power is supplied through the metal contact structure to an active region and a gate electrode that are formed on a substrate. However, the active region formed of silicon (Si) and the gate electrode formed of polysilicon (Poly-Si) have very high resistances, making it difficult to supply power to the transistor. To solve such a problem, a silicidation process is required to lower the resistances of silicon and polysilicon.
The silicidation process includes forming a silicide layer on a source/drain region and a gate electrode of a transistor so as to facilitate the power supply to the transistor. An example of the silicidation process is disclosed in U.S. Pat. No. 6,376,320 B1 entitled “Method for Forming Field Effect Transistor with Silicides of Different Thickness and of Different Materials for the Source/Drain and the Gate.” By way of the silicidation process, a silicide layer is used to decrease the resistances of a source/drain region formed of silicon and a gate electrode formed of polysilicon.
However, as the design rule of a semiconductor device is reduced to 0.1 μm or less, a typical silicidation process does not lead to reduction of resistance because it is difficult to form a metal silicide layer to a desired thickness. During the silicidation process, the silicide layer is selectively formed only in a contact region between a metal layer deposited for silicidation and silicon (or polysilicon). However, because the size of the contact region also decreases with reduction in the design rule, the silicide layer formed in the contact region cannot be used to decrease the resistance.
More specifically, the silicidation process uses a silicide MSix generated by a reaction between silicon atoms and metal atoms. Considering such a silicidation process, sufficient silicon source must be supplied to obtain a sufficient silicide. However, as the design rule is reduced to 0.1 μm or less, it becomes very difficult to supply sufficient silicon source.
For instance, the U.S. Pat. No. 6,376,320 B1 proposes a method of forming a silicide layer on a gate electrode after the top surface of the gate electrode is exposed. In this case, as the design rule is reduced to 0.1 μm or less, the width of the gate electrode is also reduced to 0.1 μm or less. Thus, since a metal layer for a silicide layer is formed only on the top surface of the gate electrode, a contact region between the metal layer and polysilicon is limited to the top surface of the gate electrode. As a result, as the width of the gate electrode is reduced to 0.1 μm or less due to the design rule, the top surface of the gate electrode and the contact region are also greatly narrowed.
A reduction in the contact area between the gate electrode and the metal layer limits the supply of a silicon source from the gate electrode, thereby making it difficult to form a sufficiently thick metal silicide layer on the gate electrode. To alleviate such a problem, the silicidation process may be performed at a higher temperature for a longer duration of time. However, this may adversely affect the reliability of a silicide layer formed on a source/drain region, as in the U.S. Pat. No. 6,376,320 B1.
Further, the amount of silicon source supplied during the silicidation reaction greatly depends on the contact area between the metal layer and silicon. Thus, even if the silicidation process is performed at a higher temperature for a longer duration of time, it is difficult to grow a silicide layer to a sufficient thickness.
Therefore, when the width of a gate electrode is reduced to 0.1 μm or less with reducing design rule, in order to lower the resistance of the gate electrode, a new method of forming a thick silicide layer on the gate electrode formed of polysilicon is required. To form a thick silicide layer on a gate electrode having a line width of 0.1 μm or less, first, a silicon source should be sufficiently supplied during a silicidation process. Also, to supply sufficient silicon source, a contact region between a metal layer formed for silicidation and a gate electrode must be greatly expanded.